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hy57v56820b(l)t 4 banks x 8m x 8bit synchronous dram this document is a general product descripti on and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 1.4/mar. 02 1 description the hy57v56820b is a 268,435,456bit cmos synchronous dram, ideally suited for the main memory applications which require large memory density and high bandwidth. the hy57v56820b is organized as 4banks of 8,388,608x8. the hy57v56820b is offering fully synchronous operation referenced to a positive edge of the clock. all inputs and outputs are synchro- nized with the rising edge of the clock input. the data paths are internally pipelined to achieve very high bandwidth. all inpu t and output voltage levels are compatible with lvttl. programmable options include the length of pipeline (read latency of 2 or 3), the number of consecutive read or write cycles in itiated by a single control command (burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). a burs t of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (this pipelined design is not restricted by a `2n` rule.) features ? single 3.3 0.3v power supply ? all device pins are compatible with lvttl interface ? jedec standard 400mil 54pin tsop-ii with 0.8mm of pin pitch ? all inputs and outputs referenced to positive edge of system clock ? data mask function by dqm ? internal four banks operation ? auto refresh and self refresh ? 8192 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4, 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency ; 2, 3 clocks ordering information part no. clock frequency power organization interface package hy57v56820bt-6 166mhz normal 4banks x 8mbits x8 lvttl 400mil 54pin tsop ii hy57v56820bt-k 133mhz hy57v56820bt-h 133mhz hy57v56820bt-8 125mhz hy57v56820bt-p 100mhz hy57v56820bt-s 100mhz HY57V56820BLT-6 166mhz low power HY57V56820BLT-k 133mhz HY57V56820BLT-h 133mhz HY57V56820BLT-8 125mhz HY57V56820BLT-p 100mhz HY57V56820BLT-s 100mhz
hy57v56820b(l)t rev. 1.4/mar. 02 2 pin configuration pin description pin pin name description clk clock the system clock input. all other input s are registered to the sdram on the rising edge of clk cke clock enable controls internal clock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh cs chip select enables or disables all inputs except clk, cke and dqm ba0, ba1 bank address selects bank to be activated during ras activity selects bank to be read/written during cas activity a0 ~ a12 address row address : ra0 ~ ra12, column address : ca0 ~ ca9 auto-precharge flag : a10 ras , cas , we row address strobe, column address strobe, write enable ras , cas and we define the operation refer function truth table for details dqm data input/output mask controls output buffers in read mode and masks input data in write mode dq0 ~ dq7 data input/output multiplexed data input / output pin v dd /v ss power supply/ground power supply for internal circuits and input buffers v ddq /v ssq data output power/ground power supply for output buffers nc no connection no connection v ss dq7 v ssq v ddq dq6 v ssq dq5 v ddq dq4 v ss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v dd dq0 v ddq dq1 v ssq dq2 v ddq dq3 v ssq v dd /we /cas /ras /cs ba0 ba1 a10/ap a0 a1 a2 a3 v dd 54pin tsop ii 400mil x 875mil 0.8mm pin pitch nc nc nc nc nc nc nc nc nc
hy57v56820b(l)t rev. 1.4/mar. 02 3 functional block diagram 8mbit x 4banks x 8 i/o synchronous dram state machine a0 a1 a12 ba0 ba1 address buffers address registers mode registers row pre decoders column pre decoders column add counter row active column active burst counter data out control cas latency x decoders internal row counter dq0 dq1 dq6 dq7 refresh self refresh logic & timer pipe line control i/o buffer & logic bank select sense amp & i/o gate clk cke cs ras cas we dqm x decoders x decoders memory cell array y decoders x decoders 8mx8 bank1 8mx8 bank0 8mx8 bank2 8mx8 bank3
hy57v56820b(l)t rev. 1.4/mar. 02 4 absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability dc operating condition (ta=0 to 70 c ) note : 1.all voltages are referenced to v ss = 0v 2.v ih (max) is acceptable 5.6v ac pulse width with 3ns of duration 3.v il (min) is acceptable -2.0v ac pulse width with 3ns of duration ac operating condition (ta=0 to 70 c , v dd =3.3 0.3v, v ss =0v) note : 1. output load to measure access time is equi valent to two ttl gates and one capacitor (50pf) for details, refer to ac/dc output circuit parameter symbol rating unit ambient temperature t a 0 ~ 70 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd, v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1w soldering temperature ? time t solder 260 ? 10 c ? sec parameter symbol min typ. max unit note power supply voltage v dd , v ddq 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 3.0 v dd + 0.3 v 1,2 input low voltage v il - 0.3 0 0.8 v 1,3 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voutref 1.4 v output load capacitance for access time measurement cl 50 pf 1
hy57v56820b(l)t rev. 1.4/mar. 02 5 capacitance (ta=25 c , f=1mhz) output load circuit dc characteristics i (ta=0 to 70 c , v dd =3.3 0.3v) note : 1.v in = 0 to 3.6v, all other pins are not tested under v in =0v 2.d out is disabled, v out =0 to 3.6v parameter pin symbol -6/k/h -8/p/s unit minmaxminmax input capacitance clk c i1 2.5 3.5 2.5 4.0 pf a0 ~ a12, ba0, ba1, cke, cs , ras , cas , we , udqm, ldqm ci 2 2.5 3.8 2.5 5.0 pf data input / output capacitance dq0 ~ dq15 c i/o 4.0 6.5 4.0 6.5 pf parameter symbol min. max unit note input leakage current i li -1 1 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -4ma output low voltage v ol -0.4vi ol = +4ma vtt=1.4v rt=250 ? 50pf output 50pf output dc output load circuit ac output load circuit
hy57v56820b(l)t rev. 1.4/mar. 02 6 dc characteristics ii (ta=0 to 70 c , v dd =3.3 0.3v, v ss =0v) note : 1.i dd1 and i dd4 depend on output loading and cycle rates. specified values are measured with the output open 2.min. of trrc (refresh ras cycle time) is shown at ac characteristics ii 3.hy57v56820bt-6/h/8/p/s 4.HY57V56820BLT-6/h/8/p/s parameter symbol test condition speed unit note -6 -k -h -8 -p -s operating current i dd1 burst length=1, one bank active t rc t rc (min), i ol =0ma 130 120 120 120 110 110 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = 15ns 2 ma i dd2ps cke v il (max), t ck = 1 precharge standby current in non power down mode i dd2n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 30ns. all other pins v dd -0.2v or 0.2v 30 ma i dd2ns cke v ih (min), t ck = input signals are stable. 15 active standby current in power down mode i dd3p cke v il (max), t ck = 15ns 5 ma i dd3ps cke v il (max), t ck = 5 active standby current in non power down mode i dd3n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 30ns. all other pins v dd -0.2v or 0.2v 40 ma i dd3ns cke v ih (min), t ck = input signals are stable. 30 burst mode operating current i dd4 t ck t ck (min), i ol =0ma all banks active cl=3 150 130 130 130 110 110 ma 1 cl=2 140 140 140 140 120 120 auto refresh current i dd5 t rrc t rrc (min), all banks active 240 220 220 200 200 200 ma 2 self refresh current i dd6 cke 0.2v 3ma3 1.5 ma 4
hy57v56820b(l)t rev. 1.4/mar. 02 7 ac characteristics i (ac operating conditions unless otherwise noted) note : 1.assume tr / tf (input rise and fall time ) is 1ns 2.access times to be measured with input signals of 1v/ns edge rate parameter symbol -6 -k -h -8 -p -s unit note minmaxminmaxminmaxmin maxminmaxminmax system clock cycle time cas latency = 3 tck3 6 1000 7.5 1000 7.5 1000 8 1000 10 1000 10 1000 ns cas latency = 2 tck2 10 7.5 10 10 10 12 ns clock high pulse width tchw 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1 clock low pulse width tclw 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1 access time from clock cas latency = 3 tac3 - 5.4 - 5.4 - 5.4 - 6 - 6 - 6 ns 2 cas latency = 2 tac2 - 6 - 5.4 - 6 - 6 - 6 - 6 ns data-out hold time toh 2.7 - 2.7 - 2.7 - 3 - 3 - 3 - ns data-input setup time tds 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 data-input hold time tdh 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 address setup time tas 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 address hold time tah 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 cke setup time tcks 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 cke hold time tckh 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 command setup time tcs 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1 command hold time tch 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1 clk to data output in low-z time tolz 1 - 1 - 1 - 1 - 1 - 1 - ns clk to data output in high-z time cas latency = 3tohz32.75.42.75.42.75.43 63636ns cas latency = 2tohz22.75.42.75.4363 63636ns
hy57v56820b(l)t rev. 1.4/mar. 02 8 ac characteristics ii note : 1. a new command can be given trrc after self refresh exit parameter symbol -6 -k -h -8 -p -s unit note min max min max min max min max min max min max ras cycle time operation trc 60 - 60 - 65 - 68 - 70 - 70 - ns auto refresh trrc 60 - 60 - 65 - 68 - 70 - 70 - ns ras to cas delay trcd 18 - 15 - 20 - 20 - 20 - 20 - ns ras active time tras 42 100k 45 100k 45 100k 48 100k 50 100k 50 100k ns ras precharge time trp 18 - 15 - 20 - 20 - 20 - 20 - ns ras to ras bank active delay trrd 12 - 15 - 15 - 16 - 20 - 20 - ns cas to cas delay tccd 1 - 1 - 1 - 1 - 1 - 1 - clk write command to data-in delay twtl 0 - 0 - 0 - 0 - 0 - 0 - clk data-in to precharge command tdpl 2 - 2 - 2 - 2 - 2 - 2 - clk data-in to active command tdal 5-5-5-5-5-5-clk dqm to data-out hi-z tdqz 2 - 2 - 2 - 2 - 2 - 2 - clk dqm to data-in mask tdqm 0 - 0 - 0 - 0 - 0 - 0 - clk mrs to new command tmrd 2-2-2-2-2-2-clk precharge to data output hi-z cas latency = 3tproz33-3-3-3-3-3-clk cas latency = 2tproz22-2-2-2-2-2-clk power down exit time tpde 1 - 1 - 1 - 1 - 1 - 1 - clk self refresh exit time tsre 1 - 1 - 1 - 1 - 1 - 1 - clk 1 refresh time tref - 64 - 64 - 64 - 64 - 64 - 64 ms
hy57v56820b(l)t rev. 1.4/mar. 02 9 ibis specification i oh characteristics (pull-up) i ol characteristics (pull-down) voltage 100mhz (min) 100mhz (max) 66mhz (min) (v) i(ma) i(ma) i(ma) 3.45 -2.4 3.3 -27.3 3.0 0 -74.1 -0.7 2.6 -21.1 -129.2 -7.5 2.4 -34.1 -153.3 -13.3 2.0 -58.7 -197 -27.5 1.8 -67.3 -226.2 -35.5 1.65 -73 -248 -41.1 1.5 -77.9 -269.7 -47.9 1.4 -80.8 -284.3 -52.4 1.0 -88.6 -344.5 -72.5 0 -93 -502.4 -93 voltage 100mhz (min) 100mhz (max) 66mhz (min) (v) i(ma) i(ma) i(ma) 0000 0.4 27.5 70.2 17.7 0.65 41.8 107.5 26.9 0.85 51.6 133.8 33.3 1.0 58.0 151.2 37.6 1.4 70.7 187.7 46.6 1.5 72.9 194.4 48.0 1.65 75.4 202.5 49.5 1.8 77.0 208.6 50.7 1.95 77.6 212.0 51.5 3.0 80.3 219.6 54.2 3.45 81.4 222.6 54.9 -600 -500 -400 -300 -200 -100 0 00.511.522.533.5 voltage (v) i (ma) i oh min (66mhz) 66mhz and 100mhz pull-up i oh min (100mhz) i oh max (66 /100mhz) 0 50 100 150 200 250 00.511.522.533.5 voltage (v) i (ma) 66mhz and 100mhz pull-down i ol min (100mhz) i ol min (66mhz) i ol max (100mhz)
hy57v56820b(l)t rev. 1.4/mar. 02 10 device operating option table hy57v56820b(l)t-6 hy57v56820b(l)t-k hy57v56820b(l)t-h hy57v56820b(l)t-8 hy57v56820b(l)t-p hy57v56820b(l)t-s cas latency trcd tras trc trp tac toh 166mhz(6ns) 3clks 3clks 7clks 10clks 3clks 5.4ns 2.7ns 143mhz(7ns) 3clks 3clks 6clks 9clks 3clks 5.4ns 2.7ns 133mhz(7.5ns) 2clks 3clks 6clks 9clks 3clks 5.4ns 2.7ns cas latency trcd tras trc trp tac toh 133mhz(7.5ns) 2clks 2clks 6clks 8clks 2clks 5.4ns 2.7ns 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 3ns 100mhz(10ns) 2clks 2clks 6clks 9clks 3clks 6ns 3ns cas latency trcd tras trc trp tac toh 133mhz(7.5ns) 3clks 3clks 7clks 10clks 3clks 5.4ns 2.7ns 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 3ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 3ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz(12ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 66mhz(15ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 100mhz(10ns) 3clks 2clks 5clks 7clks 2clks 6ns 3ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns 66mhz(15ns) 2clks 2clks 4clks 6clks 2clks 6ns 3ns
hy57v56820b(l)t rev. 1.4/mar. 02 11 command truth table note : 1. exiting self refresh occurs by asyn chronously bringing cke from low to high 2. x = don t care, h = logic high, l = logic low. ba =bank address, ra = row address, ca = column address, opcode = operand code, nop = no operation command cken-1 cken cs ras cas we dqm addr a10/ ap ba note mode register set h x llllx op code no operation h x hxxx xx lhhh bank active h x l l h h x ra v read h x lhlhxca l v read with autoprecharge h write hxlhllxca l v write with autoprecharge h precharge all banks hxllhlxx hx precharge selected bank lv burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x burst-read-single- write h x lllhx a9 pin high (other pins op code) self refresh 1 entry h l lllhx x exit l h hxxx x lhhh precharge power down entry h l hxxx x x lhhh exit l h hxxx x lhhh clock suspend entry h l hxxx x x lvvv exit l h x x
hy57v56820b(l)t rev. 1.4/mar. 02 12 package information 400mil 54pin thin small outline package 11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960) 22.327(0.8790) 22.149(0.8720) 5deg 0deg 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0047) 1.194(0.0470) 0.991(0.0390) 0.80(0.0315)bsc 0.400(0.016) 0.300(0.012) unit : mm(inch) 0.150(0.0059) 0.050(0.0020)

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